Verigy 93k Tester Manual -

Precise voltage levels are critical for CMOS logic. The manual details how to set VIHcap V sub cap I cap H end-sub VILcap V sub cap I cap L end-sub VOHcap V sub cap O cap H end-sub VOLcap V sub cap O cap L end-sub for various drive and receive modes.

A standard test flow in the 93k environment follows a specific hierarchy outlined in the manual:

The heart of the 93k manual is the SmarTest documentation. SmarTest is the software suite used to develop, debug, and execute test programs. Engineers must be familiar with the following core tools: verigy 93k tester manual

Executing patterns at speed to verify logic gates.

Containing the pin electronics and cooling systems. Precise voltage levels are critical for CMOS logic

The 93k platform is designed around a scalable architecture that allows for "per-pin" resources. Unlike traditional testers that share resources across multiple pins, the 93k provides dedicated timing, levels, and pattern memory for each channel. This ensures that complex System-on-Chip (SoC) devices can be tested with maximum precision.

Measuring setup/hold times and propagation delays. Advanced Troubleshooting Tips SmarTest is the software suite used to develop,

This is a software-driven routine that adjusts for internal tester skews. It should be performed weekly or whenever the test head temperature shifts significantly.